SAR converters for analog-digital conversion are well known in the art. In particular, SAR converters are frequently used in integrated CMOS devices since they provide a wide range of achievable resolution and conversion time and have competitive power efficiency. Furthermore, SAR converters can be implemented by optimally utilizing the advantages of the CMOS technology, which are small-sized switches and capacitors having well-defined relative capacitances.
SAR converters can be designed for non-differential or differential input signals.
According to one well-known topology, differential SAR converters include at least one capacitor bank on each input signal line. Each capacitor bank has capacitors of different values, usually with a relation between the capacitances by a factor of (n=integer). Each capacitor is connected between the signal line and a first reference potential and is further associated with a switch, so that the respective capacitor can be disconnected from the first reference potential and connected to a second reference potential. In the sampling phase, a voltage level of an input signal applied to the signal lines is stored on each capacitor of the capacitor bank. In a succeeding conversion phase, the second reference potential is applied successively, i.e. from the highest capacitance to the lowest capacitance, on the capacitors while it is determined whether the resulting voltage on the input signal lines is positive or negative. The determination results are stored as result bits in a register. The capacitor bank of the capacitor on which the second reference potential is applied is selected depending on the result bit of the determination just carried out before.
According to another known topology, the capacitor banks of an differential SAR analog-digital converters may have a C-2C design wherein the capacitor ladder is formed by switched capacitances C which are coupled via a capacity with a capacitance of 2C.
The differential SAR analog-digital converter as described above has a capacitor bank on each of the input signal lines, a decision latch to receive the input signal line voltage and a logic block which adjusts the switching of the capacitor levels depending on a previous determination in the decision latch. Usually, the capacitors of the capacitor banks are all set to a negative reference potential for sampling the input signal and are partially switched to a positive reference potential in the process of conversion. When a capacitor is switched so that a positive reference potential is applied, a capacitor charge depending on the switched reference potential difference and the capacitance of the capacitor is loaded onto the respective input signal line, thereby increasing its potential. Since in the conversion phase capacitors of both capacitor banks on the input signal lines are switched the potentials of the input signal lines tend to be increased. The result is an increase of the input common mode voltage on the input signal lines applied on the decision latch. Since the input common mode voltage variation negatively affects the latch noise and the latch conversion speed, it is generally desirable to keep the input common mode as constant as possible.